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課程名稱 |
交換電路與邏輯設計
SWITCHING CIRCUIT AND LOGIC DESIGN |
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開課學期 |
98-1 |
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授課對象 |
電機工程學系 |
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授課教師 |
李建模 |
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課號 |
EE2012 |
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課程識別碼 |
901 32300 |
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班次 |
03 |
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學分 |
3 |
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全/半年 |
半年 |
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必/選修 |
必修 |
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上課時間 |
星期四6(13:20~14:10)星期五7,8(14:20~16:20) |
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上課地點 |
電二106電二106 |
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備註 |
本系優先
總人數上限：70人 |
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Ceiba 課程網頁 |
http://ceiba.ntu.edu.tw/981_logicdesign_cmli |
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課程簡介影片 |
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核心能力關聯 |
核心能力與課程規劃關聯圖 |
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課程大綱
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為確保您我的權利,請尊重智慧財產權及不得非法影印
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課程概述 |
Course Outline
1. Unit 1 Introduction: Number Systems and Conversion
2. Unit 2 Boolean Algebra
3. Unit 3 Boolean Algebra (continued)
4. Unit 4 Applications of Boolean Algebra: Minterm and Maxterm Expansions
5. Unit 5 K-Maps
6. Unit 6 Quine-McClusky Method
7. Unit 7 Multi-Level Gate Circuits: NAND and NOR Gates
8. Unit 8 Combinational Circuit Design and Simulation Using Gates
9. Unit 9 Multiplexers, Decodes and PLD
10. Unit 10 Introduction to VHDL
11. Unit 11 Latches and FFs
12. Unit 12 Registers and Counters
13. Unit 13 Analysis of Clocked Sequential Circuits
14. Unit 14 Derivation of State Graphs and Tables
15. Unit15 Reduction of State Tables-- State assignment
16. Unit 16 Sequential Circuit Design
17. Unit 20 Circuits for Arithmetic Operations |
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課程目標 |
Provide background knowledge in logic design.
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課程要求 |
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預期每週課後學習時數 |
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Office Hours |
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指定閱讀 |
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參考書目 |
C. H. Roth, Jr. Fundamentals of Logic Design, 5th edition, Thomson. 2003 |
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評量方式
(僅供參考) |
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No. |
項目 |
百分比 |
說明 |
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1. |
Participation |
2% |
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2. |
Final |
35% |
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3. |
Quiz 2 |
7% |
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4. |
Midterm |
35% |
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5. |
Quiz 1 |
4% |
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6. |
Homework |
17% |
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週次 |
日期 |
單元主題 |
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第1週 |
9/17, 18 |
Course Info
Introduction |
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第1週 |
9/18 |
Ch 2 Boolean Algebra
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第2週 |
924, 9/25 |
Ch 3 Boolean Algebra (cont’d)
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第3週 |
10/1, 10/2 |
Ch 4 Application of Boolean Algebra
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第4週 |
10/8, 10/9 |
Ch 5 Karnaugh Maps |
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第5週 |
10/15, 10/16 |
Ch 7 Multi-Level Gate Circuits
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第6週 |
10/22, 10/23 |
10/22 QUIZ#1;
Ch 8 Comb. Ckt Design (skip 8.1, 8.2)
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第7週 |
10/29, 10/30 |
Ch 9 Multiplexers Decoders and PLD
(skip 9.7) 10/29 1:20pm-3:10pm
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第8週 |
11/5, 11.6 |
11/5 出國
11/6 Verilog 3:30-6:00pm |
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第9週 |
11/12, 11/13 |
11/12 no class 6:00-7:00pm extra office hr; 11/13 midterm |
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第10週 |
11/19, 11/20 |
Ch 11 Latches and FF 1:20pm
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第11週 |
11/26, 11/27 |
Ch 12 Registers and Counters 11/26 1:20pm-3:10pm; 11/27 出國
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第12週 |
12/3, 12/4 |
Ch 13 Analysis of Clock Sequential Ckts
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第13週 |
12/10; 12/11 |
Ch 14 Derivation of State Graphs and Tables (Skip examples 2 and 3 in Sec. 14.3)
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第14週 |
12/17, 12/18 |
12/17 quiz 2; 12/18 Ch 15 Reduction of State Tables (15.1,2)
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第15週 |
12/24, 12/25 |
Ch 16 Sequential Ckt Design (16.1 to 16.4)
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第16週 |
12/31, 1/1 |
Ch 18 Circuit for Arithmetic Operation (18.1, 18.2); 1/1 happy new year |
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第17週 |
1/7; 1/8 |
review |
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第18週 |
1/14, 1/15 |
1/14 no class, 1/15 fianl exam |
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